Category of Study: Computer Engineering and VLSI

Office:  Room 319A, Essex Hall

Email:  rmusced@uwindsor.ca

Telephone:  (519) 253-3000 extension 4798

Fax:  (519) 971-3695

Education:
I’ve received my Ph.D. (2003), M.A.Sc. (1999), and B.A.Sc. (1996) degrees from the University of Windsor, Ontario in Electrical and Computer Engineering. During most of this time I was also the lab manager for the Research Centre for Integrated Microsystems, formally VLSI Research Group.

Graduate Degree History:
My Master's degree (1996-1999) was based on research to improve real-time product defect detection. This work was targeted to applications in which several Dalsa line-scan cameras are used to visually inspect a moving paper-like product for defects immediately after it has been manufactured. These cameras were connected to localized high performance computers (essentially home PCs) so that they could perform the video-processing. In the event a defect was found, that area of the product was marked as bad, or in a more severe case, the production was stopped entirely. The environment in which the product was manufactured was not environmentally adequate for the computers. PCs are not typically designed to handle the electrical noise and dust which are commonly found in manufacturing areas. In order to maintain the video bit rates, differential parallel data transfers are used to connect the cameras to the PCs. Never the less these PCs would require constant maintenance and/or replacement and therefore slow down production. This project involved moving the heavy video processing load from the localized computers into the cameras themselves. The PCs were processing the load of many cameras (up to 16). If the processing were moved to the cameras themselves, they would only need to process data at the actual video rate. The PC-like performance wouldn't be needed as the work would be distributed in the cameras. PCs are basically general processors running non-real-time operating systems and for this application they require addition buffering data acquisition boards to handle the incoming real-time data. All of this equipment can be very expensive. It was determined that selecting high volume, common electronic components would be used in order to produce a reasonably inexpensive on-board camera processing system. The final system was designed to use both a Field Programmable Gate Array (FPGA), for real-time processing, and a Digital Signal Processor (DSP), for further, more elaborate processing. To reduce the need for expensive data acquisition boards with differential parallel inputs, we decided to look at more modern technologies for high speed data transmission in electrically noisy environments. Ethernet was one of the first options examined as it offered a networking topology, however, the speed was limits to 10Mbps and the bandwidth was not always guaranteed. Another option was a new emerging technology that offered network configurations, low-cost, high-speed serial transmission at 400Mbps with a guaranteed quality of service. This technology is known as Firewire or IEEE1394 and was suited perfectly for this application and was chosen to be the transmission medium for the cameras to the PCs. The processing system was designed, layed-out on three PCB boards so that it would connect directly to the existing cameras. Once built, the software for the PC was written along with the firmware of the on board controller and they were thoroughly tested. The design worked as intended and was able to process the data at real-time with a variety of inspection algorithms, while reducing the information into more manageable data and transmitting it to the host PC. This design was a test bed for other types of research, such as real-time fuzzy logic algorithms and camera self-syncing algorithms. Some aspects of this work have been adopted by Dalsa Inc. such as the on-board FPGA, real-time compression algorithms, firmware compression algorithms, and camera self-syncing algorithms.

During my work on the above processing system, I was employed at the University of Windsor as the Lab Manager for the Research Centre for Integrated Microsystems (formally the VLSI Research Group). My duty was to design and maintain a reliable computing environment which enabled students and researchers to build various types of integrated circuits and electronic devices. This environment features industrial EDA tools from companies such as Cadence, Synopsys, Mentor Graphics, and Xilinx. I soon became the in-house experience on these design tools as I had the opportunity to learn most of their features while testing each of them for compatibility in the design environment. This experience allowed me to become involved with many other projects with other students and researchers. I became interested in different research areas as I worked on several projects related to them. One of these projects, in particular, was a new number system based on the Logarithmic Number System (LNS), known as the Double Base Number System (DBNS, later generalized to the Multi-Dimensional Logarithmic Number System, MDLNS) was developed by a post doctoral fellow while he was at the University of Windsor. Although primarily intended for cryptography applications, we had started looking at using DBNS for high-speed DSP. One of the issues with DBNS was that we could not easily move data encoded in binary into the DBNS domain. I began analyzing the problem and found a preliminary systematic method to do just this. This became the basis for my future doctoral work.

For my Doctoral degree I worked on developing generalized methods to perform what are known as difficult operations in the MDLNS. Although my initial work was for DBNS with fixed parameters, my primary goal was to create a method to solve the Binary-to-MDLNS (low bit range, approximately 32) conversion problem with a generalized MDLNS (any number of digits, any set of bases, any range). My solution to the Binary-to-MDLNS conversion requires a new CAM (content addressable memory) structure, which I refer to as a Range Addressable Look-Up Table (RALUT), that basically acts as a non-linear look up table (LUT). By using this device we can easily realize the solution for Binary-to-MDLNS any number of digits, and any set of bases. Addition and subtraction are commonly known as difficult operations in LNS and MDLNS. The simple solution is to use LUTs to map all possible inputs to all possible outputs. However, this can create impractically large tables. In my Doctoral thesis I detailed a realizable method to solve the addition and subtraction problem for single-digit, double-base MDLNS. This method involves computing and optimizing smaller tables used in these operations.
Since my work was intended to be for generalized MDLNS, I developed software based on the methods in the Binary-to-MDLNS that would find an optimal base for a multi-digit, double-base MDLNS representation. This allows us to optimize our MDLNS representation for particular applications (e.g. DSP FIR filters). Using most of the components of my Doctoral thesis, I was able to redesign a previous design of an MDLNS 8 bank filter-bank for hearing instrument applications showing significant improvements in area, routing and power.

University Teaching:
In the fall semester I teach the undergraduate course Computer Aided Analysis II (06-85-211) and the graduate course VLSI Design (06-88-531).
Computer Aided Analysis II places an emphasis on the understanding of algorithms for numerical methods. Previous courses, such as Algebra and Calculus, examine solving problems based on pure analytical methods. In the real world, most engineering problems require the use of very large systems of equations, non-linearities, and complicated geometries in order to be practically solved. This course concentrates on some of the most commonly used numerical methods in engineering. These include finding the roots of equations, solving systems of linear algebraic equations, applying least squares curve fitting, performing numeric integration, and solving ordinary differential equations. Since all of these methods are computationally intensive and generally require many steps before an acceptable solution is determined, we implement them in software. Our programming language of choice is C/C++ as it is the basis for most object orientated languages.

In the winter semester I teach the undergraduate courses Analog Integrated Circuit Design (06-88-444) and CAPSTONE design (06-88-400).
For Analog Integrated circuit design, we emphasis the understanding of analog circuit building blocks and how they are used to design and construct larger, such as operation amplifiers, comparators, A/D converters, multipliers, wave-shaping circuits. To simplify the device models and their operation, we will be primarily examining bipolar transistors. Although CMOS transistors are quite common in todays analog IC design, they are often difficult to tune to a particular task as their operating ranges can be quite specific. Bipolar transistors offer simpler models and therefore simpler understanding of their first-order operation. We are fortunate to have a fast turn-around semi-custom analog bipolar fabrication service available from Gennum Corporation, in Burlington and coordinated by the Canadian Microelectronics Corporation, in Kingston. All students in this course will be able to layout and test their own integrated circuit.
The Capstone design course gives the 4th year students significant design experience and builds on the knowledge and skills acquired in earlier course work. It provides an exposure to teamwork so as to emulate a typical professional design environment. Computers are used both in the execution of the design methodology and the management of the design project. There are many opportunities to use appropriate knowledge and information to enable professionally mature decision-making in a team environment. This ability is essential to the design process that characterizes the practice of engineering. This course lasts from the winter to the summer semester (two semesters).

Journal Publications:
R. Muscedere, V. S. Dimitrov, G. A. Jullien, W. C. Miller, “Efficient Techniques for Binary to Multi-Digit Multi-Dimensional Logarithmic Number System Conversion using Range Addressable Look-Up Tables”, IEEE Transactions on Computers, Special Issue on Computer Arithmetic, August 2005.

S. H. Hajimowlana, R. Muscedere, G. A. Jullien, J. W. Roberts, 1999, “A Novel Approach for Defect Detection in Web Inspection”, Journal of Vision (SME publication), Vol. 15, No. 4, pp. 1-4.

S. H. Hajimowlana, R. Muscedere, G. A. Jullien, J. W. Roberts, 1999, “An In-Camera Data Stream Processing System for Defect Detection in Web Inspection Tasks”, Special Issue on Real-Time Defect Detection, Journal of Real-Time Imaging, 5, 1999, pp. 23-34.

Conference Publications:
R. Muscedere, G. A. Jullien, V. S. Dimitrov and W. C. Miller, “Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems using Arrays of Range Addressable Look-Up Tables”, Proceedings of the 2002 IEEE conference on Application-Specific Systems, Architectures, and Processors, pp. 130-138.

I. Cem Baykal, R. Muscedere, G. A. Jullien, “On the use of Hash Functions for Defect Detection in Textures for In-Camera Web Inspection Systems”, Proceedings of the 2002 International Symposium on Circuits and Systems, V, 2002, pp. 665-668.

J. Eskritt, R. Muscedere, G. A. Jullien, V. S. Dimitrov and W. C. Miller. “A 2-Digit DBNS Filter Architecture.” Proceedings of the 2000 IEEE Workshop on Signal Processing Systems (SiPS 2000), Lafayette, LA, October 2000, pp. 447-456

H. Li, R. Muscedere, V. S. Dimitrov and G. A. Jullien, “The Application of 2-D Logarithms to Low-power Hearing-aid Processor”, 45th IEEE International Midwest Symposium on Circuits and Systems, August 4-7, 2002, Tulsa, Oklahoma, Vol. 3, pp. 13-16.

R. Muscedere, G. A. Jullien, V. S. Dimitrov and W. C. Miller, “Non-Linear Signal Processing using Index Calculus DBNS Arithmetic”, Proceedings of the 2000 SPIE conference on Advanced Algorithms and Architectures in Signal Processing, San Diego, August 2000, pp. 247-257.

R. Muscedere, G. A. Jullien, V. S. Dimitrov and W. C. Miller, “On Efficient Techniques for Difficult Operations in One and Two-digit DBNS Index Calculus”, 34th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Proceedings, 2000, pp. 870-874.

S.H. Hajimowlana, G.A. Jullien, R. Muscedere, J.W. Roberts, “Defect Detection in Web Inspection Systems Using Fuzzy Fusion of Texture Features”, ISCAS 2000, IEEE International Symposium on Circuits and Systems May 28-31, Geneva, Switzerland, pp. 718-721.

S. H. Hajimowlana, R. Muscedere, G. A. Jullien, J. W. Roberts, “1D Auto regressive modeling for defect detection in web inspection systems”, Proceedings of Midwest Symposium on Circuits and Systems, Vol.1, 1998, pp. 330-333.

M. Shahkarami, G. A. Jullien, W. C. Miller, R. Muscedere, “General Purpose FIR Filter Arrays Using Optimized Redundancy Over Direct Product Polynomial Rings”, 1998 Asilomar Conference on Systems, Signals and Computation, November 1998.

S. H. Hajimowlana, R. Muscedere, G. A. Jullien, J. W. Roberts, “Efficient preprocessing algorithms for an FPGA based in camera video stream processing for bandwidth reduction in web inspection”, IEEE Canadian Conference on Electrical and Computer Engineering, Vol.2, May 25-28, 1997, pp. 835-838.

S. H. Hajimowlana, R. Muscedere, G. A. Jullien, J. W. Roberts, “A New Design Environment for Defect Detection in Web Inspection Systems”, Proceedings of machine vision applications in industrial inspection, SPIE, Vol. 3204, August 1997, pp. 125-136.