DRAM Architecture Design and Analysis with DRAMSys (1st Offering)
Presenter: Sadra Hakim
Date: Monday, November 10, 2025
Time: 11:00 am
Location: Workshop Space, 4th Floor - 300 Ouellette Ave., School of Computer Science Advanced Computing Hub
This workshop focuses on exploring and reasoning about DRAM architectural configurations using DRAMSys. Participants will dive deeper into how memory controllers, scheduling policies, and address mapping strategies influence latency, bandwidth, and row-buffer efficiency. The session also covers interpreting DRAMSys outputs such as command statistics, timing breakdowns, and utilization metrics to justify architectural trade-offs in AI inference workloads. Attendees will also learn how to compare and present results effectively, as well as how to connect simulation metrics to system-level performance and design reasoning for DRAM configurations under both CPU and GPU inference scenarios.
- Brief tour of internal concepts, including controller and mapping components
- Analyzing simulation and metrics on different configs
- Learn to present configuration–performance trade-offs clearly in reports
Familiarity with Python and Linux commands would help, but is not required.
Sadra is a Ph.D. student in Computer Science at the University of Windsor, where his research focuses on applying machine learning and deep learning models to biomedical challenges.