Dylan Lalonde, M.A.Sc.
2017, Private and Public-Key Side-Channel Threats Against Hardware Accelerated Cryptosystems
This work delivers a novel design, analysis, and successful results from a custom differential power analysis attack on AES-128. The resulting SCA can break any 16-byte master key the sophisticated cipher uses and it’s direct applications towards public-key cryptosystems will become clear. Further, the architecture of a SCA resistant scalar point algorithm accompanied by an implementation of an optimized serial multiplier will be constructed.
The optimized hardware design of the multiplier is highly modular and can use either NIST approved 233 & 283-bit Kobliz curves utilizing a polynomial basis.
Yue Huang, M.A.Sc.
2016, Efficient Scalar Multiplication Against Side Channel Attacks Using New Number Representation
The classic algorithm for computation of elliptic curve scalar multiplication is Doubling-and-Add. However, it has been shown vulnerable to simple power analysis. Although Montgomery power ladder (MPL) has shown to be a good choice for scalar multiplication against simple power analysis, it is still subject to some advanced SCAs such as differential power analysis. In this work, a new number representation is proposed which is used for scalar multiplication algorithms. It has also been shown that the proposed algorithms outperform or are comparable with the the state-of-the-art in terms of against side channel attacks and computational efficiency.
Yuan Jing, M.A.Sc.
2016, An Efficient FPGA Implementation of Optical Character Recognition System for License Plate Recognition
Optical Character Recognition system (OCR) can be used in intelligent transportation systems for license plate detection. However, most times the systems are unable to work with noisy and imperfect images. In this work, a robust FPGA-based OCR system has been designed and tested with imperfect and noisy license plate images. The OCR system is based on a feed orward neural networks, which uses an efficient and precise neuron. The neuron transfer function is based on an approximation of the Hyperbolic Tangent Activation Function. The neuron is utilized in a 189-160-36 feed forward neural network configuration. The network parameters were optimized an then tested with noisy images of license plates numbers. The network was able to maintain a 98:2% accuracy in recognizing the characters despite the image imperfections.
Rani Gnanaolivu, Post Doctorate Fellow
2014, Scheduling for Flexible Manufacturing using Knowledge-Based Intelligent Systems
Production scheduling tasks in manufacturing environments is an important and challenging task. Automatic production scheduler allocates available resources over time for performing a collection of operations. Job-shop scheduling is one of the most complicated types of scheduling. It is a process where limited resources, such as machines, material and tooling, are allocated over the time horizon among both parallel and sequential activities.A suitable solution to job-shop scheduling can be application of intelligent, knowledge-based systems.
Babak Zamanlooy, Ph.D.
2014, Mixed-Signal VLSI Implementation of CVNS Artificial Neural Networks
In this work, mixed-signal implementation of Continuous Valued Number System (CVNS) neural network is proposed. The proposed network resolves the limited signal processing precision issue present in mixed-signal neural networks. This is realized by the CVNS addition, the CVNS multiplication and the CVNS sigmoid function evaluation algorithms proposed in this dissertation. The proposed algorithms provide accurate results in low-resolution environment.
In addition, an area-efficient low sensitivity CVNS Madaline is proposed. The proposed Madaline is more robust to input and weight errors when compared to the previously developed structures. Moreover, its area consumption is lower. Furthermore, a new approximation scheme for hyperbolic tangent activation function is proposed. Using the proposed approximation scheme results in the efficient implementation of digital ASIC neural networks in terms of area, delay and power consumption.
Farinoush Saffar, M.A.Sc.
2013, Mixed-Signal Feed-Forward Neural Network Architecture using High-Resolution Multiplying D/A Converter
In this thesis, a mixed-signal neural network architecture is proposed using novel high resolution Multiplying Digital to Analog Converter (MDAC) modules in which digital synaptic weights are converted to analog using Delta Sigma Modulation (DSM) technique. Using this method, high resolution synaptic weights stored in registers are encoded into time domain to maintain high accuracy synaptic calculations for the neural network. Arithmetic operations, such as addition and multiplication, are performed in analog domain to reduce the amount of required circuitry. In addition to that, multiplexing method is used to compensate for the increased overhead area due to high resolution components.
Ashley Novak, M.A.Sc.
2013, Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Application
Due to the ubiquity of electronic communication systems in consumers’ lives, it is necessary to ensure that the sensitive information being transmitted is not accessible by malicious parties. Because of advancements in technology, it is now possible to easily steal data from these electronic systems, even if they are protected by a strong encryption algorithm. These security threats, known as Side Channel Attacks, have exposed weaknesses in the hardware architectures of the systems meant to be secure. This research explores a novel method of designing a crypto processor component, the adder, which allows it to produce minimal side channel information, rendering it less vulnerable in terms of hardware. The results show that it is possible to maintain a competitively low power consumption, as compared to conventional architectures, all while providing a method to greatly improve data security systems.
Iman Makaremi, Post Doctorate Fellow
2012, Investigation of an On-Line Inspection System for Airbag Quality Control
Golnar Khodabandehloo, Ph.D.
2011, A Prototype CVNS Distributed Neural Network
In this work, Continuous Valued Number System (CVNS) distributed neural networks are proposed which are providing the network with self-scaling property. This property aids the network to cope spontaneously with different number of inputs. The proposed CVNS DNN can change the dynamic range of the activation function spontaneously according to the number of inputs providing a proper functionality for the network. In addition, multi-valued CVNS DRAMs are proposed to store the weights as CVNS digits. These memories scan store up to 16 level, equal to 4 bits, on each storage cell. In addition, they use error correction codes to detect and correct the error over the stored values.
A synapse-neuron module is proposed to decrease the design cost. It contains both synapse and neuron and the relevant components. In these modules, the activation function is realized through analog circuits which are far more compact compared to the digital look-up-tables while quite accurate. Furthermore, the redundancy between CVNS digits, together with the distributed structure of the neuron make the proposal stable against process variations and reduce the noise to signal ratio.